Technical Field
The present disclosure relates to the field of semiconductor technology, and more particularly to a nanowire device and method of manufacturing the same.
Description of the Related Art
As the size of microelectronic devices scales below the 15 nm node, challenges in semiconductor device fabrication arise. For example, it becomes increasingly difficult to maintain/improve carrier mobility and control short channel effects with device scaling.
Nanowire devices, for example semiconductor devices having channel lengths on the nanometer scale, can provide improved carrier mobility and short channel control. For example, a germanium channel can help to increase the carrier mobility of a p-channel metal oxide semiconductor (PMOS) transistor, whereas a channel formed of a Group III-V semiconductor material can help to increase the carrier mobility of an n-channel metal oxide semiconductor (NMOS) transistor.
During the manufacture of a nanowire device, an isotropic etching process is commonly used to remove the dummy gate material below the nanowire. However, nanowire devices obtained using the isotropic etching process typically do not have consistent gate contour profiles above and below the nanowire. As a result, it may be difficult to meet specific gate contour profile requirements in the nanowire devices.